Dynamic process window control using simulated wet data from current and previous layer data
US5866437A · kind A · utility
60Cited by
3References
1Claims
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Key dates
| Filing date | Dec 5, 1997 |
| Grant date | Feb 2, 1999 |
| Priority date | — |
| Expiry date | Dec 5, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing semiconductor wafers using a simulation tool to determine predicted wafer electrical test measurements. The simulation tool combines in-line critical dimensions from previous from previous processes run on the current wafer lot, data from previous lots for processes subsequent to the process being run on the current lot and calibration simulation data obtained from the comparison of the predicted wafer electrical test measurements and collected wafer electrical test measurements taken from previous actual wafer electrical test measurements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.