High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate
US5866952A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1995 |
| Grant date | Feb 2, 1999 |
| Priority date | — |
| Expiry date | Nov 30, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high density interconnected multi-chip module is provided with a stress-reducing compliant material disposed around the chips prior to molding a polymeric substrate around the chips. Chips having contact pads are placed face down on a layer of adhesive supported by a base. A compliant material is deposited around the chips, and then a mold form is positioned around the chips. Polymeric substrate molding material is added within the mold form, and then the substrate molding material is hardened. A dielectric layer having vias aligned with predetermined ones of the contact pads and having an electrical conductor extending through the vias is situated on the hardened substrate molding material and faces of the chips. A thermal plug may be affixed to the backside of a chip prior to the addition of substrate molding material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.