Integrated circuit memory device having reduced stress across large on-chip capacitor
US5867421A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1997 |
| Grant date | Feb 2, 1999 |
| Priority date | — |
| Expiry date | Oct 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit memory device (10) includes a large on-chip capacitor (12) that has a high voltage plate and a low voltage plate. The large on-chip capacitor (12) stores charge for a positive voltage supply (VPP) for the integrated circuit memory device (10). The high voltage plate of the large on-chip capacitor (12) is connected to a node (NODE 1) for distributing charge from the large on-chip capacitor. A load (16) is connected to the node (NODE 1) and consumes charge from the high voltage plate to power operations of the integrated circuit memory device (10). The load (16) includes a memory array comprising a plurality of memory cells. The low voltage plate of the large on-chip capacitor (12) is connected to a capacitive voltage reference which has high capacitance and has a voltage-level greater than ground potential and less than the positive voltage supply. In one embodiment, the large on-chip capacitor is a storage/filter capacitor (12) for a boosted high voltage supply (VPP), and the capacitive voltage reference is a memory cell reference voltage (VPLT) which is also connected to a reference plate of memory cell capacitors (28) of the memory cells (20) in the memory a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.