Method for forming insulating layers between polysilicon layers
US5869406A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1995 |
| Grant date | Feb 9, 1999 |
| Priority date | — |
| Expiry date | Sep 28, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/909
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an integrated circuit device with a substantially uniform inter-layer dielectric layer. The method includes steps of providing a partially completed semiconductor wafer (400) where the partially completed semiconductor device has a first polysilicon layer (401) thereon. The method includes depositing a dielectric layer (405) overlying the polysilicon layer and portions of the partially completed semiconductor device at a pressure of about 1 atmosphere. A step of forming a second polysilicon layer overlying portions of the dielectric layer is also included. The dielectric layer depositing step includes combining an organic silane and an ozone at a concentration of 200 g/m.sup.3 and less.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.