Multi-bank memory input/output line selection
US5870347A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 1997 |
| Grant date | Feb 9, 1999 |
| Priority date | — |
| Expiry date | Mar 11, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-bank memory includes memory cells arranged in individually selectable banks that share column select signals. The memory cells are addressed by a row decoder that activates word lines to couple data onto digit lines. The digit lines are coupled to input/output lines through first and second series-connected switches. The first switches are input/output switches that are controlled by column select signals that are shared between multiple banks. The second switches are bank select switches that are controlled by a bank decoder, for coupling only one of the banks to input/output lines and isolating the other banks from input/output lines. The invention reduces timing requirements between operations in different banks, and allows concurrent operations in different banks, thereby increasing the speed at which the memory operates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.