Inventor · Boise, ID, US

Brent Keeth

334Patents
50h-index
125Co-inventors
93Inventor score

Filing activity: Mar 26, 1993 → Dec 12, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US5935263A Method and apparatus for memory array compressed data testing Physics 472 Expired
US6029250A Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same Physics 440 Expired
US6442644B1 Memory system having synchronous-link DRAM (SLDRAM) devices and controller Emerging Cross-Sectional Technologies 382 Expired
US6016282A Clock vernier adjustment Physics 328 Expired
US8106520B2 Signal delivery in stacked device Emerging Cross-Sectional Technologies 285 Active
US6011732A Synchronous clock generator including a compound delay-locked loop Physics 241 Expired
US6256234A Low skew differential receiver with disable feature Electricity 213 Expired
US6661041B2 Digitline architecture for dynamic memory Physics 204 Expired
US5838177A Adjustable output driver circuit having parallel pull-up and pull-down elements Physics 192 Expired
US6430696B1 Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same Physics 182 Expired
US6103547A High speed IC package configuration Electricity 178 Expired
US6697926B2 Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device Physics 164 Expired
US5949254A Adjustable output driver circuit Electricity 163 Expired
US6434081B1 Calibration technique for memory devices Physics 161 Expired
US6101197A Method and apparatus for adjusting the timing of signals over fine and coarse ranges Physics 156 Expired
US5870347A Multi-bank memory input/output line selection Physics 143 Expired
US5920518A Synchronous clock generator including delay-locked loop Electricity 139 Expired
US6662304B2 Method and apparatus for bit-to-bit timing correction of a high speed memory bus Physics 137 Expired
US5852378A Low-skew differential signal converter Electricity 131 Expired
US5901105A Dynamic random access memory having decoding circuitry for partial memory blocks Physics 129 Expired
US5917758A Adjustable output driver circuit Electricity 121 Expired
US6043562A Digit line architecture for dynamic memory Physics 119 Expired
US6069504A Adjustable output driver circuit having parallel pull-up and pull-down elements Physics 105 Expired
US6133622A High speed IC package configuration Electricity 105 Expired
US6115318A Clock vernier adjustment Physics 102 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.