Method and apparatus for on die testing
US5870408A · kind A · utility
7Cited by
8References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1996 |
| Grant date | Feb 9, 1999 |
| Priority date | — |
| Expiry date | Apr 30, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318505
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Circuits and methods of testing an integrated circuit die are disclosed. Active logic setting circuits are incorporated into input cells of a die. During testing, the active logic setting circuits weakly drive the input cells to a definite logic level. Therefore, the necessity of connecting probes to all of the input pads to prevent floating signals in the die is eliminated. Furthermore, during normal operations the active logic setting circuits have little or no effect on the performance of the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.