Method of fabricating DRAM capacitors
US5874335A · kind A · utility
24Cited by
2References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 23, 1998 |
| Grant date | Feb 23, 1999 |
| Priority date | — |
| Expiry date | Feb 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A method for fabricating a semiconductor device is provided comprising forming a dual silicon nitride spacer to be an etching step layer during a self-aligned contact etching step. The invention discloses a bottom electrode with a tri-forked structure and a hemispherical grain layer of a capacitor, therefore the capacitor has a larger surface area. So the capacitor made by the invention has a high capacitance even though the planar surface size is reduced continually.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.