Method for planarizing TEOS SiO.sub.2 filled shallow isolation trenches
US5874345A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 1996 |
| Grant date | Feb 23, 1999 |
| Priority date | — |
| Expiry date | Nov 18, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to the present invention, there is disclosed a method for planarizing TEOS SiO.sub.2 filled shallow isolation trenches according to a planarization main step which is comprised of three processing steps. The starting structure (10) consists of a silicon substrate (11) coated by a patterned Si.sub.3 N.sub.4 layer (12) which delineates shallow trenches (20A, 20B) with a conformal layer (22) of TEOS SiO.sub.2 formed thereon. A planarizing medium, typically two superimposed photoresist layers (24.25) is formed onto the resulting structure to provide a substantially planar surface. At this stage of the fabrication, the structure is standard. Now, this planar surface is translated by a non selective two-steps plasma etching in the TEOS SiO.sub.2 layer (22). Next, should some photoresist material remain onto the structure it would be removed. Finally, a highly selective TEOS SiO.sub.2 /Si.sub.3 N.sub.4 RIE etching step is performed which stops on the Si.sub.3 N.sub.4 layer. The preferred chemistry is C.sub.4 F.sub.8 /Ar or C.sub.4 F.sub.8 /CO/Ar mixture. There is no longer the notion of process window because both the "silicon polish" and "Si.sub.3 N.sub.4 pad residuals" type of…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.