Computer hybrid memory including DRAM and EDRAM memory components, with secondary cache in EDRAM for DRAM
US5875451A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 1996 |
| Grant date | Feb 23, 1999 |
| Priority date | — |
| Expiry date | Mar 14, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system with a hybrid main memory which includes both EDRAM and DRAM, with a DRAM cache provided within a designated portion of the EDRAM portion of the main memory. Read requests are handled by copying data being read from DRAM into a cache portion of EDRAM under the direction of a pseudo cache controller and decoder which converts the DRAM address to a EDRAM address corresponding to the cache location of EDRAM. Read "hit" requests are responded to by reading data directly from the cache portion of EDRAM. Write requests to DRAM are, for purposes of cache coherency when a copy of the address being written to is present in the EDRAM cache portion, accomplished by writing data both to DRAM and overwriting the stale data existing in the cache portion of EDRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.