Lateral gate, vertical drift region transistor
US5877047A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 1997 |
| Grant date | Mar 2, 1999 |
| Priority date | — |
| Expiry date | Aug 15, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/931
Abstract
This is a method of fabricating a lateral gate, vertical drift region transistor including a semiconductor substrate having a drain on the reverse surface. A doped semiconductor layer is formed on the substrate and a high resistivity region is formed adjacent the surface of the doped layer so as to define a vertical drift region in the doped layer. A lateral channel is formed on the high resistivity region and the doped layer so as to communicate with the vertical drift region. A source is positioned on the lateral channel spaced laterally from the vertical drift region and a gate is positioned on the lateral channel between the drift region and the source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.