Metal planarization using a CVD wetting film
US5877086A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 1997 |
| Grant date | Mar 2, 1999 |
| Priority date | — |
| Expiry date | Jul 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76882
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is a process for planarization of substrate layers comprising apertures to form continuous, void-free contacts or vias in sub-half micron applications. A CVD silicon or metal silicide wetting layer is deposited onto the substrate layer comprising apertures to provide a conformal wetting layer for a PVD metal layer. The PVD metal layer is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The CVD layer diffuses into the PVD layer and the resulting conductive layer is substantially void-free. The planarization process is preferably carried out in a multi-chamber system that includes both PVD and CVD processing chambers so that once the substrate is introduced into a vacuum environment, the filling of vias and contacts occurs without the formation of an oxide layer over the CVD wetting layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.