III-V/II-VI Semiconductor interface fabrication method
US5879962A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1995 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | Dec 13, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/443
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for repeatably fabricating GaAs/ZnSe and other III-V/II-VI semiconductor interfaces with relatively low stacking fault densities in II-VI semiconductor devices such as laser diodes. The method includes providing a molecular beam epitaxy (MBE) system including at least a group III element source, a group II element source, a group V element source and a group VI element source. A semiconductor substrate having a III-V semiconductor surface on which the interface is to be fabricated is positioned within the MBE system. The substrate is then heated to a temperature suitable for III-V semiconductor growth, and a crystalline III-V semiconductor buffer layer grown on the III-V surface of the substrate. The temperature of the semiconductor substrate is then adjusted to a temperature suitable for II-VI semiconductor growth, and a crystalline II-VI semiconductor buffer layer grown on the III-V buffer layer by alternating beam epitaxy. The group II and group VI sources are operated to expose the III-V buffer layer to a group II element flux before exposing the III-V buffer layer to a group VI element flux.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.