Supratik Guha
122Patents
16h-index
114Co-inventors
89Inventor score
Filing activity: Sep 24, 1993 → Jul 22, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5739545A | Organic light emitting diodes having transparent cathode structures | Electricity | 141 | Expired |
| US5898185A | Hybrid organic-inorganic semiconductor light emitting diodes | Electricity | 96 | Expired |
| US6541079B1 | Engineered high dielectric constant oxide and oxynitride heterostructure gate dielectrics by an atomic beam deposition technique | Chemistry; Metallurgy | 95 | Expired |
| US7488656B2 | Removal of charged defects from metal oxide-gate stacks | Electricity | 73 | Expired |
| US7105889B2 | Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics | Electricity | 61 | Expired |
| US6210479A | Product and process for forming a semiconductor structure on a host substrate | Emerging Cross-Sectional Technologies | 56 | Expired |
| US6255671A | Metal embedded passivation layer structure for microelectronic interconnect formation, customization and repair | Electricity | 42 | Expired |
| US5895932A | Hybrid organic-inorganic semiconductor light emitting diodes | Electricity | 41 | Expired |
| US7242055B2 | Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide | Electricity | 38 | Expired |
| US6852575B2 | Method of forming lattice-matched structure on silicon and structure formed thereby | Electricity | 35 | Expired |
| US8138102B2 | Method of placing a semiconducting nanostructure and semiconductor device including the semiconducting nanostructure | Electricity | 30 | Active |
| US6528374B2 | Method for forming dielectric stack without interfacial layer | Electricity | 27 | Expired |
| US7440281B2 | Thermal interface apparatus | Electricity | 27 | Expired |
| US7479683B2 | Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics | Electricity | 25 | Expired |
| US6146755A | High density magnetic recording medium utilizing selective growth of ferromagnetic material | Emerging Cross-Sectional Technologies | 24 | Expired |
| US7998788B2 | Techniques for use of nanotechnology in photovoltaics | Emerging Cross-Sectional Technologies | 16 | Active |
| US7750418B2 | Introduction of metal impurity to change workfunction of conductive electrodes | Electricity | 16 | Active |
| US6120909A | Monolithic silicon-based nitride display device | Chemistry; Metallurgy | 16 | Expired |
| US7219713B2 | Heterogeneous thermal interface for cooling | Electricity | 15 | Expired |
| US8604559B2 | Method of placing a semiconducting nanostructure and semiconductor device including the semiconducting nanostructure | Electricity | 14 | Active |
| US7452767B2 | Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics | Electricity | 14 | Active |
| US7446380B2 | Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS | Electricity | 14 | Expired |
| US6831339B2 | Aluminum nitride and aluminum oxide/aluminum nitride heterostructure gate dielectric stack based field effect transistors and method for forming same | Electricity | 13 | Expired |
| US8193051B2 | Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics | Electricity | 13 | Active |
| US7329361B2 | Method and apparatus for fabricating or altering microstructures using local chemical alterations | Emerging Cross-Sectional Technologies | 12 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.