Semiconductor chips having a mesa structure provided by sawing

US5882986A · kind A · utility

Assignee

• General Semiconductor, Inc. · US

Inventors

• Jack Eng · Freeport, US
• Joseph Chan · San Francisco, US
• Willem G. Einthoven · Montgomery, US
• John Amato · Tracy, US
• Sandy Tan · Farmingdale, US
• Lawrence LaTerza · Miller Place, US
• Gregory Zakaluk · Seaford, US
• Dennis Garbis · Huntington Station, US

Key dates

• Filing date: Mar 30, 1998
• Grant date: Mar 16, 1999
• Expiry date: Mar 30, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/3043
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Starting with a semiconductor wafer of known type including an internal, planar p-n junction parallel to major surfaces of the wafer, one of the wafer surfaces is covered with a masking layer of silicon nitride. A plurality of intersecting grooves are then sawed through the masking layer for forming a plurality of mesas having sloped walls with each mesa including a portion of the planar p-n junction having edges which intersect and are exposed by the mesa walls. The groove walls and exposed junction edges are glass encapsulated in a process including heating the wafer. The masking layers are then removed in a selective etching process not requiring a patterned etchant mask, and the now exposed silicon surfaces at the top of the mesas, as well as the opposite surface of the wafer, are metal plated. The wafer is then diced along planes through the grooves for providing individual chips each having a glass passivated mesa thereon.