Clock frequency detector for a synchronous memory device
US5883853A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 1997 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Nov 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention employs a clock frequency detector in a SDRAM that detects whether an input clock signal is operating at a fast rate (e.g., 125 MHz or a 8 nanosecond access time), or at a slower rate. In response to the input clock frequency, the clock frequency detector outputs a selection signal to control logic circuitry in the SDRAM indicating whether the SDRAM should operate in either a fast or slow mode. The clock frequency detector employs a frequency detector that detects the frequency of the input clock signal. Based on the frequency of the input clock signal, a selector circuit outputs either a fast or slow selection signal to the control logic circuitry. In response to the fast selection signal, the control logic circuitry performs data access commands at a fast rate, while in response to the slow selection signal, the control logic circuitry executes such commands at a slower, more conservative rate. As a result, the SDRAM device can operate according to its maximum specifications in connection with a fast input clock rate (allowing essentially no margins for error), or perform at a slower rate based on a slower input clock frequency (allowing for some margin of e…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.