Pattern data compression and decompression for semiconductor test system
US5883906A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 1997 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Aug 15, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31908
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A compression and decompression apparatus to be used for transferring test pattern data from a storage device of a host computer to a pattern memory in a semiconductor test system for testing a semiconductor device to decrease the time required for the data transfer. The compression and decompression apparatus includes: a compression means for classifying vector data in the test pattern data into a first group to be compressed to a short code and a second group not to be compressed, and for producing a look-up table showing relationship between the short code and the vector data in the first group; a compressed test pattern file storing compressed test pattern including the short code, data vector in the second group and the look-up table; and a hardware decompression circuit provided in the semiconductor test system or proximity thereto for decompressing the compressed test pattern based on the short code and the relationship shown in the look-up table and for sending decompressed test pattern to the pattern memory in the semiconductor test system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.