System, methods and computer program products for flexibly controlling bus access based on fixed and dynamic priorities
US5884051A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 1997 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Jun 13, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Bus performance in a computer system having multiple devices accessing a common shared bus may be improved by providing a flexible bus arbiter. Bus access is controlled using a bus arbiter which is operationally connected to each of the devices. Each device has a fixed programmable priority level and a dynamic priority level associated with it. The dynamic priority level comprises an arbiter dynamic priority level and a master dynamic priority level. Access to the bus by a device is controlled based on the combination of the programmable fixed priority level and the dynamic priority level associated with each device. While the programmable fixed priority level and the arbiter dynamic priority level as set by the arbiter are not controlled by the master, the master dynamic priority level is controlled by the master. If master dynamic priority is enabled, it overrides the arbiter dynamic priority level. If master dynamic priority is not enabled but arbiter dynamic priority is enabled, master dynamic priority overrides the programmable fixed priority level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.