Low-latency, high-throughput, integrated cache coherent I/O system for a single-chip processor
US5884100A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1996 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Jun 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-chip central processing unit (CPU) includes a processing core and a complete cache-coherent I/O system that operates asynchronously with the processing core. An internal communications protocol uses synchronizers and data buffers to transfer information between a clock domain of the processing core and a clock domain of the I/O system. The synchronizers transfer control and handshake signal between clock domains, but the data buffer transfers data without input or output synchronization circuitry for data bits. Throughput for the system is high because the processing unit has direct access to I/O system so that no delays are incurred for complex mechanisms which are commonly employed between a CPU and an external I/O chip-set. Throughput is further increased by holding data from one DMA transfer in the data buffer for use in a subsequent DMA transfer. In one embodiment, the integrated I/O system contains a dedicated memory management unit including a translation lookaside buffer which converts I/O addresses to physical addresses for the processing core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.