Method of customizing integrated circuits by selective secondary deposition of layer interconnect material
US5885749A · kind A · utility
255Cited by
10References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 20, 1997 |
| Grant date | Mar 23, 1999 |
| Priority date | — |
| Expiry date | Jun 20, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating custom integrated circuits includes the steps of 1) patterning a photoresist layer on an insulative layer with a standard via precision mask to define all possible vias, and 2) using a targeting energy beam to select the desired via locations, which are then etched and interconnections made, for customization or repair of the integrated circuit. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.