Inventor · Fremont, CA, US

John MacPherson

20Patents
10h-index
13Co-inventors
68Inventor score

Filing activity: Nov 29, 1988 → Nov 28, 2006

Most-cited inventions

PatentTitleAreaCited byStatus
US5885749A Method of customizing integrated circuits by selective secondary deposition of layer interconnect material Electricity 255 Expired
US5223154A System for filtering liquids in a catch basin using filters in series and overflow channels Fixed Constructions 88 Expired
US5017394A Method for making edible base shapes having pictorial images for decorating foodstuffs Human Necessities 62 Expired
US6311316A Designing integrated circuit gate arrays using programmable logic device bitstreams Physics 55 Expired
US6749748B1 Methods for reducing the amount of contaminants in water Chemistry; Metallurgy 24 Expired
US6348742B1 Sacrificial bond pads for laser configured integrated circuits Electricity 23 Expired
US6078091A Inter-conductive layer fuse for integrated circuits Electricity 17 Expired
US6821427B2 Methods for reducing the amount of contaminants in water Chemistry; Metallurgy 14 Expired
US6060330A Method of customizing integrated circuits by selective secondary deposition of interconnect material Electricity 11 Expired
US6486527B1 Vertical fuse structure for integrated circuits containing an exposure window in the layer over the fuse structure to facilitate programming thereafter Electricity 10 Expired
US5985518A Method of customizing integrated circuits using standard masks and targeting energy beams Electricity 9 Expired
US6096566A Inter-conductive layer fuse for integrated circuits Electricity 8 Expired
US5945238A Method of making a reusable photolithography mask Physics 8 Expired
US6020648A Die structure using microspheres as a stress buffer for integrated circuit prototypes Electricity 7 Expired
US5989783A Method of customizing integrated circuits by depositing two resist layers to selectively pattern layer interconnect material Emerging Cross-Sectional Technologies 7 Expired
US6369437B1 Vertical fuse structure for integrated circuits and a method of disconnecting the same Electricity 5 Expired
US6235556A Method of improving parallelism of a die to package using a modified lead frame Electricity 3 Expired
US6239480A Modified lead frame for improved parallelism of a die to package Electricity 3 Expired
US6087200A Using microspheres as a stress buffer for integrated circuit prototypes Electricity 1 Expired
US7749391B2 Coagulant-enhanced pre-filtration system Chemistry; Metallurgy 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.