Issuing instructions in a processor supporting out-of-order execution
US5887161A · kind A · utility
40Cited by
24References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1997 |
| Grant date | Mar 23, 1999 |
| Priority date | — |
| Expiry date | Mar 31, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method for issuing instructions in a processor. In one version of the invention, the method includes the steps of dispatching the instruction and source information to a queue, determining validity of the source information, and issuing the instruction for execution in response to the source information validity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.