Memory device having circuitry for initializing and reprogramming a control operation feature
US5887162A · kind A · utility
73Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 13, 1997 |
| Grant date | Mar 23, 1999 |
| Priority date | — |
| Expiry date | Jan 13, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous dynamic random access memory (SDRAM) device having a master control circuit for accepting a first command and a second command and having an initialization and reprogramming circuit. The master control circuit generates an initialization signal in response to the first command and generates a reprogramming signal in response to the second command. The initialization and reprogramming circuit responds to the initialization signal to control initial programming of a control operation feature and responds to the reprogramming signal to control a reprogramming of the control operation feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.