Method of fabricating a gate array semiconductor integrated circuit device
US5891765A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 1997 |
| Grant date | Apr 6, 1999 |
| Priority date | — |
| Expiry date | Jan 13, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
In order to improve a withstand voltage and implement a gate array SOI semiconductor integrated circuit device having a large gate width, a region consisting of end cells (49) is provided on each end of a region formed by repeatedly arranging basic cells (BC) consisting of both transistor regions (32, 33) in a first direction and while symmetrically arranging the same to be folded in a second direction. Both ends of a channel region of a PMOS transistor (42) are drawn out in the second direction to provide a P-type semiconductor layer just under a field shielding gate electrode (FG), and this semiconductor layer is drawn also in the first direction to be connected with a P-type semiconductor layer of the end cell (49). A first source potential is applied to a region (PBD) which is bonded with one of the P-type semiconductor layers. Also as to an NMOS transistor (41) which is adjacent through a field oxide film (FO), on the other hand, an N-type semiconductor layer is similarly provided so that this N-type semiconductor layer is also connected with that of the end cell (49). A second source potential is applied to a region (NBD).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.