Method for fabricating an asymmetric channel doped MOS structure
US5891782A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Aug 21, 1997 |
| Grant date | Apr 6, 1999 |
| Priority date | — |
| Expiry date | Aug 21, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6757
Abstract
A method of forming a MOS transistor without a lightly doped drain (LDD) region between the channel region and drain is provided. The channel region is formed from a tilted ion implantation after the deposition of the gate oxide layer. The tilted implantation forms a relatively short channel length, with respect to the length of the gate electrode. The position of the channel is offset, and directly adjoins the source. The non-channel area under the gate, adjacent the drain, replaces the LDD region between the channel and the drain. This drain extension acts to more evenly distribute electric fields so that large breakdown voltages are possible. The small channel length, and eliminated LDD region adjacent the source, act to reduce resistance between the source and drain. In this manner, larger I.sub.d currents and faster switching speeds are obtained. A MOS transistor having a short, offset channel and drain extension is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.