Transistor fabrication method
US5891784A · kind A · utility
37Cited by
12References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1995 |
| Grant date | Apr 6, 1999 |
| Priority date | — |
| Expiry date | Apr 27, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/952
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. An anti-reflective coating helps protect against reflective gate notching. A variety of silicided and non-silicided) structures may be formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.