Method of forming a zero layer mark for alignment in integrated circuit manufacturing process employing shallow trench isolation
US5893744A · kind A · utility
59Cited by
7References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 28, 1997 |
| Grant date | Apr 13, 1999 |
| Priority date | — |
| Expiry date | Jan 28, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an alignment mark in a wafer during the manufacture of shallow isolation trenches for semiconductor devices provides a nitride layer on a substrate prior to the formation of the alignment mark. Once the nitride layer has been formed, etching is performed to create the alignment mark in the substrate. Further processing steps of the shallow trench isolation technique do not require the depositing of nitride into the alignment mark. Since the alignment mark is etched only after the nitride layer has been deposited, no further nitride enters into the alignment mark and a nitride-free alignment mark is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.