Larry Wang
42Patents
16h-index
35Co-inventors
81Inventor score
Filing activity: Aug 8, 1994 → Jun 24, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6037671A | Stepper alignment mark structure for maintaining alignment integrity | Emerging Cross-Sectional Technologies | 61 | Expired |
| US5893744A | Method of forming a zero layer mark for alignment in integrated circuit manufacturing process employing shallow trench isolation | Emerging Cross-Sectional Technologies | 59 | Expired |
| US6087243A | Method of forming trench isolation with high integrity, ultra thin gate oxide | Emerging Cross-Sectional Technologies | 55 | Expired |
| US5930645A | Shallow trench isolation formation with reduced polish stop thickness | Electricity | 54 | Expired |
| US6171962A | Shallow trench isolation formation without planarization mask | Electricity | 38 | Expired |
| US6150243A | Shallow junction formation by out-diffusion from a doped dielectric layer through a salicide layer | Electricity | 32 | Expired |
| US5963816A | Method for making shallow trench marks | Electricity | 30 | Expired |
| US5926723A | Generation of a loose planarization mask having relaxed boundary conditions for use in shallow trench isolation processes | Electricity | 30 | Expired |
| US6074927A | Shallow trench isolation formation with trench wall spacer | Electricity | 26 | Expired |
| US6100145A | Silicidation with silicon buffer layer and silicon spacers | Electricity | 23 | Expired |
| US6238986A | Formation of junctions by diffusion from a doped film at silicidation | Electricity | 22 | Expired |
| US6239031A | Stepper alignment mark structure for maintaining alignment integrity | Emerging Cross-Sectional Technologies | 21 | Expired |
| US5485097A | Method of electrically measuring a thin oxide thickness by tunnel voltage | Electricity | 20 | Expired |
| US6096599A | Formation of junctions by diffusion from a doped film into and through a silicide during silicidation | Emerging Cross-Sectional Technologies | 17 | Expired |
| US6383906B1 | Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption | Electricity | 16 | Expired |
| US6130467A | Shallow trench isolation with spacers for improved gate oxide quality | Electricity | 16 | Expired |
| US6124183A | Shallow trench isolation formation with simplified reverse planarization mask | Electricity | 13 | Expired |
| US6323516A | Flash memory device and fabrication method having a high coupling ratio | Electricity | 13 | Expired |
| US6143624A | Shallow trench isolation formation with spacer-assisted ion implantation | Emerging Cross-Sectional Technologies | 13 | Expired |
| US6599810B1 | Shallow trench isolation formation with ion implantation | Electricity | 13 | Expired |
| US6162689A | Multi-depth junction formation tailored to silicide formation | Electricity | 13 | Expired |
| US6169005A | Formation of junctions by diffusion from a doped amorphous silicon film during silicidation | Electricity | 10 | Expired |
| US5970362A | Simplified shallow trench isolation formation with no polish stop | Electricity | 10 | Expired |
| US5970363A | Shallow trench isolation formation with improved trench edge oxide | Electricity | 10 | Expired |
| US6232635A | Method to fabricate a high coupling flash cell with less silicide seam problem | Electricity | 8 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.