Microelectronic package including a polymer encapsulated die, and method for forming same
US5895229A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 1997 |
| Grant date | Apr 20, 1999 |
| Priority date | — |
| Expiry date | May 19, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic package (10) is formed and includes an integrated circuit die (12) attached to a substrate (14) by a plurality of solder bump interconnections (16) to form a preassembly (18). The integrated circuit die (12) has an active face (20) that faces the substrate (14) and is spaced apart therefrom by a gap (22). The integrated circuit die (12) also includes a back face (24) opposite the active face (20). The substrate (14) includes a die attach region (26) and a surrounding region (28) about the integrated circuit die (12). The solder bump interconnections (16) extend across the gap (22) and connect the integrated circuit die (12) and the substrate (14). A mold (30) is disposed about the preassembly (18) such that the mold (30) cooperates with the substrate (14) to define a mold cavity (32) that encloses the integrated circuit die (12). The mold (30) has a molding surface (34) that includes the surrounding region (28) and a mold surface (34) that faces the back face (24) and is spaced apart therefrom. A polymeric precursor (36) is dispensed into the mold cavity (32) and is formed against the molding surface (34) and the back face (24). The polymeric precursor (36) is the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.