Method and a system for fixing hold time violations in hierarchical designs
US5896299A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1995 |
| Grant date | Apr 20, 1999 |
| Priority date | — |
| Expiry date | Oct 13, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a computer implemented process for fixing hold time violations in hierarchical designs of electronic circuits. The process comprises the steps of: PA1 1) synthesizing a RTL-HDL type description of the circuit to form a synthesized design, PA1 2) synthesizing a clock tree and adding it to the synthesized design produced in step 1, PA1 3) optimizing the synthesized design resulting from step 2, and fixing upper-bounded timing constraints by using a real clock timing (latency and skew) and worst case conditions, PA1 4) fixing lower-bounded timing violations in the optimized synthesized design resulting from step 3, using a real clock timing, using best case conditions, PA1 5) re-fixing possible upper-bounded timing constraints newly created and possible upper-bounded timing constraints increased in step 4, PA1 6) fixing post-layout upper-bounded timing violations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.