Circuits and methods for multi-level data through a single input/ouput pin
US5896337A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 1998 |
| Grant date | Apr 20, 1999 |
| Priority date | — |
| Expiry date | Feb 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and memory circuits for increasing the data bandwidth per microprocessor operation cycle is provided. The memory circuits provide the additional bandwidth without additional input/output (I/O) pins or requiring decreased cycle times. Multiple bits of data are passed through a single input/output pin with each operation cycle. The multiple bits of data are stored in or retrieved from multiple memory cells in each cycle. The I/O pins carry analog signals which represent multiple values of binary data. This method of compressing data can be applied to any device that would benefit from the ability to transfer more data through a limited number of I/O pins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.