Multiple array architecture for analog or multi-bit-cell memory
US5896340A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 1997 |
| Grant date | Apr 20, 1999 |
| Priority date | — |
| Expiry date | Jul 7, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory architecture divides memory cells of a memory into multiple memory arrays where each memory array has local row and column lines that are directly coupled to memory cells in the memory array and electrically isolated from other arrays. Continuous global row and column lines cross the memory arrays. The memory additionally includes global decoders that apply operating voltages to the global lines corresponding to a selected memory cell being access. Local decoders decode bits from the address signal to select an array containing the selected memory cell and connect the global lines to the selected memory array. Other memory arrays are disconnected from the global lines to avoid disturbance that would result from the operating voltage being applied to unselected memory cells. Alternative, embodiments include a memory including a row of memory arrays, or a column of memory arrays, or multiple rows and multiple columns of memory arrays. Another alternative embodiment has continuous global column, row, and source lines and local source lines. Global decoding circuitry applies a source bias voltage to the global source lines which local source decoders apply to the local source …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.