System and method for selecting shorted wordlines of an array having dual wordline drivers
US5898637A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 1997 |
| Grant date | Apr 27, 1999 |
| Priority date | — |
| Expiry date | Jan 6, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system including an array of memory cells connected along wordlines and bitlines, wordline driver circuitry for driving at least two selected wordlines simultaneously in response to multirow selection bits, and selection bit circuitry for asserting multirow selection bits to the wordline driver circuitry in response to address bits (or address bits and control bits) to cause simultaneous selection of a target wordline and at least one other wordline shorted with the target wordline, and wordline selection methods performed by such a system. Preferably, the selection bit circuitry includes a predecoder implemented as a logic circuit, and the wordline driver circuitry includes a row decoder, a set of wordline drivers for driving even-numbered wordlines, and another set of wordline drivers for driving odd-numbered wordlines. The predecoder preferably includes an odd wordline predecoder for asserting selection bits for selecting at least one odd wordline of an erase block, and an even wordline predecoder for asserting selection bits for selecting at least one even wordline of the erase block. The system preferably includes a controller which generates a set of address bits for…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.