Method of reducing loading variation during etch processing

US5899706A · kind A · utility

Assignees

• Siemens Aktiengesellschaft · DE
• International Business Machines Corporation · US

Inventors

• Andreas Kluwe · South Burlington, US
• Lars Liebmann · Poughquag, US
• Frank Prein · Glen Allen, US
• Thomas Zell · Dresden, DE

Key dates

• Filing date: Jun 30, 1997
• Grant date: May 4, 1999
• Expiry date: Jun 30, 2017

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/926
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In preparation for etch processing a semiconductor chip having areas of little or no pattern and areas that are heavily patterned, adding non-operative patterns to the areas having little or no pattern so that the overall pattern density is about the same across the chip.