Dynamic random access memory having decoding circuitry for partial memory blocks
US5901105A · kind A · utility
Inventors
Key dates
| Filing date | Jun 5, 1997 |
| Grant date | May 4, 1999 |
| Priority date | — |
| Expiry date | Jun 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor dynamic random-access memory (DRAM) device embodying numerous features that collectively and/or individually prove beneficial and advantageous with regard to such considerations as density, power consumption, speed, and redundancy is disclosed. The device is a 64 Mbit DRAM comprising eight substantially identical 8 Mbit partial array blocks (PABs), each pair of PABs comprising a 16 Mbit quadrant of the device. Between the top two quadrants and between the bottom two quadrants are column blocks containing I/O read/write circuitry, column redundancy fuses, and column decode circuitry. Column select lines originate from the column blocks and extend right and left across the width of each quadrant. Each PAB comprises eight substantially identical 1 Mbit sub-array blocks (SABs). Associated with each SAB are a plurality of local row decoder circuits functioning to receive partially decoded row addresses from a column predecoder circuit and generating local row addresses supplied to the SAB with which they are associated. Various pre- and/or post-packaging options are provided for enabling a large degree of versatility, redundancy, and economy of design. Programmable optio…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.