Method for utilizing a single multiplex address bus between DRAM, SRAM and ROM
US5901298A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1996 |
| Grant date | May 4, 1999 |
| Priority date | — |
| Expiry date | Oct 7, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory interface device for interfacing between the local bus and a memory bus. The memory bus is coupled to a static memory and a dynamic memory. The interface device includes first and second internal buses coupled to a selecting device. The selecting device selectively couples one of the first and second internal buses to the memory bus. The memory interface device further includes an interface control unit having an input coupled to the local bus for receiving address and control signals. The interface control unit further has an output, coupled to the first internal bus for generating gating each data transfer in the burst in response to the address and control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.