Methods for forming an intermetallic region between a solder bump and an under bump metallurgy layer and related structures
US5902686A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 21, 1996 |
| Grant date | May 11, 1999 |
| Priority date | — |
| Expiry date | Nov 21, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/1259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method for forming a solder bump on a substrate include the steps of forming an under bump metallurgy layer on a substrate, forming a solder bump on the under bump metallurgy layer, and forming an intermetallic portion of the under bump metallurgy layer adjacent the solder bump. In particular, the solder bump has a predetermined shape and this predetermined shape is retained while forming the intermetallic portion of the under bump metallurgy layer. This predetermined shape preferably has a flat surface opposite the substrate thus providing a uniform thickness of solder during the formation of the intermetallic portion. Related structures are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.