Memory device with multiple internal banks and staggered command execution
US5903509A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 1998 |
| Grant date | May 11, 1999 |
| Priority date | — |
| Expiry date | May 4, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1039
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory device such as a page-oriented synchronous dynamic random access memory device (SDRAM), a memory array and associated circuitry are divided into multiple internally defined circuit banks. Commands and addresses applied to the memory device affect all internal banks identically, but on a time-staggered basis. In an eight bank embodiment, activation of a selected row is first initiated in Bank0 by registration of an ACTIVE command and a coincident row address. One system clock cycle later, activation of the selected row is initiated in Bank1, and so on until activation of the selected row is initiated in Bank7 seven clock cycles after the initial registration of the command. A READ or WRITE command and coincident column address can be applied after the activation time limit has been met for the selected row in Bank0. The READ or WRITE command then affects successive banks in the above-described time staggered manner. Similarly, a PRECHARGE command can be applied when the read latency or write recovery time limit has been met for Bank0, and this command is executed in a time staggered manner in the successive banks. In a four bank embodiment, command registration and execu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.