Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system
US5905876A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1996 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Dec 16, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A transaction ordering mechanism for processor-based computing systems ensures proper ordering of transactions between the processor, I/O and memory subsystems, ensures cache coherence within the computing system, and facilitates concurrence of the transactions so as to enable high-bandwidth, deadlock-free operation. I/O to memory transactions and processor to memory transactions are placed in a memory request queue in the order in which such transactions appear on the processor bus; I/O to memory transactions are placed in an inbound request queue in the order such transactions appear on the I/O bus; and processor to I/O transactions and completions corresponding to split-transaction I/O to memory read transactions are placed in an outbound request queue in the order in which the split-transaction I/O to memory read transactions and the processor to I/O transactions appear on the processor bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.