Mask write enablement for memory devices which permits selective masked enablement of plural segments
US5907512A · kind A · utility
83Cited by
13References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 1993 |
| Grant date | May 25, 1999 |
| Priority date | — |
| Expiry date | Oct 20, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Mask Write mode for a semiconductor memory responds to an enable command. This permits a by-four chip to provide parity information for four sectors of memory. The invention allows the latching of mask data on a rising edge of CAS so that new mask data can be entered in Page Mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.