Fabrication method for reduced-dimension FET devices
US5908307A · kind A · utility
94Cited by
6References
38Claims
0Family size
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Key dates
| Filing date | Jan 31, 1997 |
| Grant date | Jun 1, 1999 |
| Priority date | — |
| Expiry date | Jan 31, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/061
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Pre-amorphization of a surface layer of crystalline silicon to an ultra-shallow (e.g., less than 100 nm) depth provides a solution to fabrication problems including (1) high thermal conduction in crystalline silicon and (2) shadowing and diffraction-interference effects by an already fabricated gate of a field-effect transistor on incident laser radiation. Such problems, in the past, have prevented prior-art projection gas immersion laser doping from being effectively employed in the fabrication of integrated circuits comprising MOS field-effect transistors employing 100 nm and shallower junction technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.