Method of forming low capacitance interconnect structures on semiconductor substrates
US5908318A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1997 |
| Grant date | Jun 1, 1999 |
| Priority date | — |
| Expiry date | Sep 17, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a method for forming an interconnect line having low conductor line capacitance between devices formed on an integrated circuit. The method comprises the steps of depositing a removable planarizing layer over fabricated device on the integrated circuit, depositing a first oxide layer over the planarizing layer, etching pillar shafts through the planarizing layer and the first oxide layer for the formation of pillars, depositing a second oxide layer over the first oxide layer filling the pillar shafts to form the pillars, etching contact shafts through the planarizing layer, the first oxide layer, and the second oxide layer to expose contacts for a first device and a second device formed on the integrated circuit, forming an electrical coupling between the contacts of the first device and the second device, etching through the planarizing layer, the first oxide layer, and the second oxide layer to provide accesses to the planarizing layer, removing the planarizing layer to form cavities separated by the pillars and the contact shafts, sealing the accesses to the cavities with a third oxide layer, and introducing an inert ambiance while sealing the accesses to the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.