MOSFET having buried shield plate for reduced gate/drain capacitance
US5912490A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 1997 |
| Grant date | Jun 15, 1999 |
| Priority date | — |
| Expiry date | Aug 4, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Gate to drain capacitance in a lateral DMOS and vertical DMOS field effect transistor is minimized by providing a conductive shield plate under the gate and between the gate and the drain of the transistor. In operation, the shield plate is preferably connected to a DC voltage potential and coupled to AC ground for RF power applications. The shield plate is readily fabricated in a conventional polysilicon gate process by adding one additional polysilicon deposition (or other suitable material), one additional mask, and one additional etch step. The shield plate can include a raised portion which provides lateral capacitive isolation between the gate and the drain. Alternatively, a shield contact can be provided above the shield plate and between the gate and drain to provide lateral isolation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.