Method of fabricating a capacitor structure for a dynamic random access memory
US5913129A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 1998 |
| Grant date | Jun 15, 1999 |
| Priority date | — |
| Expiry date | Jan 12, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A method of fabricating a capacitor structure for a dynamic random access memory. This method comprises the following steps: a transistor is provided on a semiconductor substrate, and spacers are formed over the sidewalls of a gate electrode of the transistor. A first oxide layer is formed over the transistor. A bit line is deposited to contact with the source region of the transistor. Thereafter, a second oxide layer is formed over the bit line. A contact opening is formed exposing the drain region. Then the hemispherical grained silicon layer is formed into the contact opening. A polysilicon layer is formed over the hemispherical grained silicon layer. Therefore both the hemispherical grained silicon layer and the third polysilicon layer have rough surfaces. Subsequent conventional processes for the complete formation of capacitor structure are performed. It is therefore the capacitor maintains a required capacitance while reducing the horizontal dimensions of the storage capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.