Methods for filling trenches in a semiconductor wafer
US5915190A · kind A · utility
283Cited by
15References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 30, 1997 |
| Grant date | Jun 22, 1999 |
| Priority date | — |
| Expiry date | Jul 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02274
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for filling a trench in a semiconductor wafer that is disposed in a plasma-enhanced chemical vapor deposition chamber. The method includes the step of depositing a protection layer of silicon dioxide over the wafer and into the trench while the wafer is biased at a first RF bias level. The protection layer has a thickness that is insufficient to completely fill the trench. Further, there is provided the step of forming a trench-fill layer of silicon dioxide over the protection layer and into the trench while the wafer is biased at a second RF bias level that is higher than the first bias level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.