Ion implantation process to improve the gate oxide quality at the edge of a shallow trench isolation structure
US5915195A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1997 |
| Grant date | Jun 22, 1999 |
| Priority date | — |
| Expiry date | Nov 25, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor fabrication process comprising forming a dielectric on an upper surface of a single crystal silicon substrate. A trench mask is then patterned on an upper surface of the dielectric. The trench mask exposes portions of the dielectric situated over portions of the isolation region. Exposed portions of the dielectric are then removed and portions of the silicon within the isolation region are also removed to form an isolation trench within the silicon substrate. This formation results in the formation of corners in the silicon substrate where the upper surface of the silicon substrate intersects with sidewalls of the isolation trench. Localized damage is then created in regions proximal to these corners of the silicon substrate preferably through the use of one or more ion implantation processes performed at implant angles in excess of approximately 30.degree. C. During the subsequent formation of a liner oxide on the sidewalls and floor of the isolation trench, the localized damage region results in a higher oxidation rate of the silicon substrate proximal to the silicon substrate corners. This higher oxidation rate results in a rounding or smoothing of the silicon co…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.