Charles E. May
118Patents
24h-index
47Co-inventors
90Inventor score
Filing activity: Nov 27, 1974 → Jan 14, 2010
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6225168A | Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof | Electricity | 160 | Expired |
| US6210999A | Method and test structure for low-temperature integration of high dielectric constant gate dielectrics into self-aligned semiconductor devices | Electricity | 135 | Expired |
| US6452412B1 | Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography | Electricity | 110 | Expired |
| US6150222A | Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions | Electricity | 81 | Expired |
| US5963803A | Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths | Electricity | 61 | Expired |
| US6130012A | Ion beam milling to generate custom reticles | Physics | 56 | Expired |
| US5943585A | Trench isolation structure having low K dielectric spacers arranged upon an oxide liner incorporated with nitrogen | Electricity | 48 | Expired |
| US6008095A | Process for formation of isolation trenches with high-K gate dielectrics | Electricity | 48 | Expired |
| US6323519A | Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process | Electricity | 46 | Expired |
| US6268637A | Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication | Electricity | 42 | Expired |
| US6067154A | Method and apparatus for the molecular identification of defects in semiconductor manufacturing using a radiation scattering technique such as raman spectroscopy | Physics | 42 | Expired |
| US6084280A | Transistor having a metal silicide self-aligned to the gate | Electricity | 42 | Expired |
| US6410967B1 | Transistor having enhanced metal silicide and a self-aligned gate electrode | Electricity | 39 | Expired |
| US6560504B1 | Use of contamination-free manufacturing data in fault detection and classification as well as in run-to-run control | Emerging Cross-Sectional Technologies | 35 | Expired |
| US6207485A | Integration of high K spacers for dual gate oxide channel fabrication technique | Electricity | 35 | Expired |
| US6274442A | Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making same | Electricity | 35 | Expired |
| US6100173A | Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process | Electricity | 34 | Expired |
| US6150708A | Advanced CMOS circuitry that utilizes both sides of a wafer surface for increased circuit density | Electricity | 34 | Expired |
| US6144071A | Ultrathin silicon nitride containing sidewall spacers for improved transistor performance | Emerging Cross-Sectional Technologies | 33 | Expired |
| US5882983A | Trench isolation structure partially bound between a pair of low K dielectric structures | Electricity | 27 | Expired |
| US6140674A | Buried trench capacitor | Electricity | 27 | Expired |
| US6087705A | Trench isolation structure partially bound between a pair of low K dielectric structures | Electricity | 25 | Expired |
| US5915195A | Ion implantation process to improve the gate oxide quality at the edge of a shallow trench isolation structure | Electricity | 25 | Expired |
| US6005285A | Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device | Electricity | 25 | Expired |
| US6151119A | Apparatus and method for determining depth profile characteristics of a dopant material in a semiconductor device | Electricity | 24 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.