Flash memory with high speed erasing structure using thin oxide semiconductor devices
US5917757A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1997 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | Jun 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory with a high speed erasing structure includes a bank of flash transistors having a plurality of wordlines, a plurality of bitlines and a sourceline. A wordline decoder is coupled to the wordlines and configured to selectively apply voltages to the wordlines to perform procedures on the flash transistors, where the procedures include a read procedure, an erase procedure and a program procedure. During the erase procedure, the wordline decoder is configured to apply a first increasingly negative voltage in a first voltage range to at least one selected wordline until a first threshold voltage is met, then to apply a second increasingly negative voltage in a second voltage range to the selected wordline and to simultaneously apply a third negative voltage in a third voltage range to at least one deselected wordline. Another embodiment of the invention increases the selected sourceline voltage to achieve a high voltage differential between the gate and source of flash transistors selected to be erased. Advantages of the invention include a fast erasing procedure due to the increased voltage differential applied between the gate and source of flash transistors selected to …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.