APLUS FLASH TECHNOLOGY, INC.
109Patents
51Active
109Granted
48Portfolio score
Filing activity: Mar 18, 1997 → Dec 27, 2015 · 17 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7164608B2 | NVRAM memory cell architecture that integrates conventional SRAM and flash cells | Physics | 346 | Expired |
| US5953255A | Low voltage, low current hot-hole injection erase and hot-electron programmable flash memory with enhanced endurance | Physics | 126 | Expired |
| US5978283A | Charge pump circuits | Electricity | 117 | Expired |
| US6381670B1 | Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation | Physics | 103 | Expired |
| US6714457B1 | Parallel channel programming scheme for MLC flash memory | Physics | 88 | Expired |
| US6031765A | Reversed split-gate cell array | Physics | 74 | Expired |
| US5835420A | Node-precise voltage regulation for a MOS memory system | Physics | 63 | Expired |
| US6620682B1 | Set of three level concurrent word line bias conditions for a nor type flash memory array | Electricity | 61 | Expired |
| US6556481B1 | 3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell | Physics | 60 | Expired |
| US6862223B1 | MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT | Physics | 59 | Expired |
| US8120959B2 | NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same | Physics | 55 | Active |
| US6023188A | Positive/negative high voltage charge pump system | Electricity | 50 | Expired |
| US6498752B1 | Three step write process used for a nonvolatile NOR type EEPROM memory | Physics | 46 | Expired |
| US7369438B2 | Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications | Electricity | 46 | Expired |
| US6757196B1 | Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device | Electricity | 43 | Expired |
| US6009022A | Node-precise voltage regulation for a MOS memory system | Physics | 43 | Expired |
| US5920503A | Flash memory with novel bitline decoder and sourceline latch | Physics | 40 | Expired |
| US6850438B2 | Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations | Physics | 40 | Expired |
| US9171627B2 | Non-boosting program inhibit scheme in NAND design | Physics | 38 | Active |
| US5978277A | Bias condition and X-decoder circuit of flash memory array | Physics | 38 | Expired |
| US5917757A | Flash memory with high speed erasing structure using thin oxide semiconductor devices | Physics | 36 | Expired |
| US6788612B2 | Flash memory array structure suitable for multiple simultaneous operations | Physics | 32 | Expired |
| US8773903B2 | High speed high density nand-based 2T-NOR flash memory design | Electricity | 32 | Active |
| US6240027A | Approach to provide high external voltage for flash memory erase | Physics | 31 | Expired |
| US6660585B1 | Stacked gate flash memory cell with reduced disturb conditions | Physics | 26 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.