Apparatus and method for instruction fetching using a multi-port instruction cache directory
US5918044A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1996 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | Oct 31, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an instruction fetch unit for an information handling system which decodes instructions, calculates target addresses of multiple branch instructions, and resolves multiple branch instructions in parallel instead of sequentially, the critical path through a multiple way set associative instruction cache is through a directory and compare circuit which selects which way instructions will be retrieved. This patch is known as the late select path. A multi-ported effective address (EA) directory is provided and is accessed prior to selection of a fetch address which fetches the next set of instructions from the cache. In this manner, the time required for the late select path can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.